Microsemi's SmartFusion2 SoC FPGA is a low-power FPGA device that integrates a fourth-generation flash-based FPGA fabric, 166MHz ARM Cortex-M3 processor and high-performance communication interface, making it the industry's lowest power, most reliable and safest. Logic solution. High-speed serial interface including PCIe, 10Gbps additional unit interface (XAUI) / XGMII) and SerDes communication, mainly used in data security, motor control, system management, industrial automation, high-speed serial I / O applications, PCIe, , SGMII and user-defined serial interface. This article describes the main features of the SmartFusion2 SoC FPGA, block diagram and chip layout, and the main features, block diagram, circuit diagram, bill of materials and PCB design of the SmartFusion2 SoC FPGA evaluation board M2S090TS-EVAL-KIT. 2.0mm (0.079") Pitch Pin Headers
Pin header customization is also available upon your request. The 2.0mm pitch pin header is highly recommendable for signal and low power PC board connections when space is at a premium and when 1.0mm and 1.27mm pitch headers cannot dissipate the required current. In addition, the 2.0mm pitch pin header holds an excellent mating quality that fits with various types of female connectors.
Industrial and Automotive Control and Test
2.0mm pitch pin (male) headers are offered in either Surface-mount or Through-hole mount termination. At one side of this pin header is a series of pins which can either be mounted and soldered directly onto the surface of the PCB (SMT) or placed into drilled holes on the PCB (THM).
2.0mm Right-angle Dual Row pin header, 2.0mm SMT Single row pin header, 2.0mm SMT Dual row pin header and 2.0mm Elevated Dual Row Pin Header are Antenk`s SMT pin headers.
Right-Angle Pin (Male) Header Orientation
Pcb Pin Header,2.0Mm Male Header,2.0Mm Male Header Pins,2.0Mm Pin Header,0.079in Male Header, 0.079in Pin Header Connector ShenZhen Antenk Electronics Co,Ltd , https://www.atkconnectors.com
Microsemi SmartFusion®2 SoC FPGAs integrate a fourth-generaTIon, flash-based FPGA fabric, an ARMCortex-M3 processor, and high-performance communicaTIons interfaces on a single chip. TheSmartFusion2 family is the industry's lowest-power, most reliable, and highest- Security programmablelogic soluTIon.
SmartFusion2 SoC FPGAs offer up to 3.6X the gate density and up to 2X the performance of previous flash-based FPGA families, and also include mulTIple memory blocks and multiply-accumulate blocks for DSP processing. The 166-MHz ARM Cortex-M3 processor is enhanced with An embedded tracemacrocell (ETM), a memory protection unit (MPU), an 8-KB instruction cache, and additional peripherals, including controller area network (CAN), gigabit Ethernet, and a high-speed universal serial bus (USB).
High-speed serial interfaces include PCI Express (PCIe), 10-Gbps Attachment Unit Interface (XAUI)/XGMII extended sublayer (XGXS), plus native serialization/deserialization (SerDes) communication. The DDR2/DDR3 memory controllers available in the devices provide High-speedmemory interfaces.
Key features of SmartFusion2 SoC FPGA:
The following sections list the features of SmartFusion2 SoC FPGAs.
Reliability
• Single event upset (SEU)-immune
• Zero FIT FPGA configuration cells
• Junction temperature
• 125 °C—military temperature
• 100 °C—industrial temperature
• 85 °C—commercial temperature
• 125 °C—automotive
• Single error correct double error detect (SECDED) protection on the following:
• Ethernet buffers
• CAN message buffers
• Cortex-M3 embedded scratch pad memory (eSRAMs)
• USB buffers
• PCIe buffer
• DDR memory controllers with optional SECDED modes
• Buffers implemented with SEU resistant latches on the following:
• DDR bridges (MSS, MDDR, and FDDR)
• Instruction cache
• MMUART FIFOs
• SPI FIFOs
• NVM integrity check at power-up and on demand
• No external configuration memory required—instant-on, retains configuration when powered off
Security
• Design security features (available on all devices)
• Intellectual property (IP) protection through unique security features and use models new to thePLD industry
• Built-in CRI DPA pass-through license from Rambus Cryptography Research
• Encrypted user key and bitstream loading, enabling programming in less-trusted locations
• Supply-chain assurance device certificate
• Enhanced anti-tamper features
• Zeroization
• Data security features
• Non-deterministic random bit generator (NRBG)
• User cryptographic services (AES-256, SHA-256, and elliptical curve cryptographic (ECC)engine)
• User physical unclonable function (PUF) key enrollment and regeneration
• CRI pass-through DPA patent portfolio license
• Hardware firewalls protecting microcontroller subsystem (MSS) memories
Low Power
• Low static and dynamic power
• Flash*Freeze mode for fabric
• Power as low as 13 mW/Gbps per lane for SerDes devices
• Up to 50% lower total power than competing SoC devices
High Performance
• Efficient 4-input look-up tables (LUTs) with carry chains for high performance and low power
• Up to 236 blocks of dual-port 18-Kbit SRAM (LSRAM) with 400 MHz synchronous performance (512
× 36, 512 × 32, 1 Kb × 18, 1 Kb × 16, 2 kbit × 9, 2 Kb × 8, 4 Kb × 4, 8 Kb × 2, or 16 Kb × 1)
• Up to 240 blocks of three-port 1-Kb SRAM with two read ports and one write port (micro SRAM)
• High-performance DSP signal processing
• Up to 240 fast mathblocks with 18 × 18 signed multiplication, 17 × 17 unsigned multiplicationand 44-bit accumulator
Microcontroller Subsystem
• Hard 166-MHz 32-Bit ARM Cortex-M3 processor
• 1.25 DMIPS/MHz
• 8 Kbyte instruction cache
• Embedded trace macrocell (ETM)
• Memory protection unit (MPU)
• Single cycle multiplication, hardware divide
• JTAG debug (4 wires), serial wire debug (SWD, 2 wires), and serial wire viewer (SWV)
Interfaces
• 64 KB embedded SRAM (eSRAM)
• Up to 512 KB embedded nonvolatile memory (eNVM)
• Triple-speed Ethernet (TSE) 10/100/1000 Mbps MAC
• USB 2.0 high speed on-the-go (OTG) controller with ULPI interface
• 2.0B-compliant CAN controller, conforms to ISO11898-1, 32 transmit and 32 receive buffers
• Two SPI ports, two I2C ports, and multi-mode UARTs (MMUART) peripherals
• Hardware-based watchdog timer
• One general-purpose 64-bit (or two 32-bit) timer(s)
• Real-time calendar/counter (RTC)
• DDR bridge (4-port data R/W buffering bridge to DDR memory) with 64-bit AXI interface
• Non-blocking, multi-layer AHB bus matrix allowing multi-master scheme supporting 10 masters and7 slaves
• Two AHB-Lite/APB3 interfaces to FPGA fabric (master/slave-capable)
• Two DMA controllers to offload data transactions from the Cortex-M3 processor
• 8-channel peripheral DMA (PDMA) for data transfer between MSS peripherals and memory
• High-performance DMA (HPDMA) for data transfer between eSRAM and DDR memories
Clocking Resources
• Clock sources
• Up to two high precision 32 KHz to 20 MHz main crystal oscillator
• 1-MHz embedded RC oscillator
• 50-MHz embedded RC oscillator
• Up to eight clock conditioning circuits (CCCs) with up to eight integrated analog PLLs
• Output clock with eight output phases and 45° phase difference (multiply/divide and delaycapabilities)
• Frequency: 1 MHz to 200 MHz input, 20 MHz to 400 MHz output
High-Speed ​​Serial Interfaces
• Up to 16 SerDes lanes, each supporting:
• XGXS/XAUI extension (to implement a 10-Gbps (XGMII) Ethernet PHY interface)
• Native EPCS SerDes interface that facilitates implementation of serial rapidIO (SRIO) in fabricor an SGMII interface to the Ethernet MAC in MSS
• PCI express (PCIe) endpoint controller
• ×1, ×2, and ×4 lane PCI express core
• Maximum payload size of up to 256 bytes
• 64-bit/32-bit AXI interface and 64-Bit/32-Bit AHB master and slave interfaces to the applicationlayer
High-Speed ​​Memory Interfaces
• Up to two high-speed DDRx memory controllers
• MSS DDR (MDDR) and fabric DDR (FDDR) controllers
• Supports LPDDR/DDR2/DDR3
• Maximum 333 MHz DDR clock rate
• SECDED enable/disable feature
• Supports various DRAM bus width modes, ×8, ×9, ×16, ×18, ×32, ×36
• Supports command reordering to optimize memory efficiency
• Supports data reordering, returning critical word first for each command
• SDRAM support through the SMC_FIC and additional soft SDRAM memory controller
Operating Voltage and I/Os
• 1.2 V core voltage
• Multi-standard user I/Os (MSIO/MSIOD)
• LVTTL/LVCMOS 3.3 V (MSIO Only)
• LVCMOS 1.2 V, 1.5 V, 1.8 V, 2.5 V
• DDR (SSTL2_1, SSTL2_2)
• LVDS, MLVDS, Mini-LVDS, RSDS differential standards
• PCI
• LVPECL (receiver only)
• DDR I/Os (DDRIO)
• DDR2, DDR3, LPDDR, SSTL2, SSTL18, HSTL
• LVCMOS 1.2 V, 1.5 V, 1.8 V, 2.5 V
• Market-leading number of user I/Os with 5G SerDes ![[Original] Microsemi Low Power SmartFusion2 SoC FPGA Development Solution](http://i.bosscdn.com/blog/14/21/01/24P_0.png)
Figure 1. SmartFusion2 SoC FPGA Block Diagram
The flash fabric also has the advantage that no external configuration memoryis required, making the device instant-on; it retains configuration when powered off. Single complement correct double error detect (SECDED) protection is implemented on the Cortex-M3 embeddedscratch pad memory, Ethernet, CAN, and USB buffers, and is optional on The DDR memory controllers.
This means that if a one-bit error is detected, the error is corrected automatically. If errors of more than one bit are detected, they are not corrected. SECDED error signals are brought to the FPGA fabric to allow the user to monitor the status of these Protected internal memories. Other areas of the architecture are implemented with latches, which are more resistant to SEUs., and no correction is needed in DDR bridges (MSS, MDDR, and FDDR), instruction cache and MMUART, SPI, and PCIe FIFOs. ![[Original] Microsemi Low Power SmartFusion2 SoC FPGA Development Solution](http://i.bosscdn.com/blog/14/21/03/3G4_0.png)
Figure 2. SmartFusion2 SoC FPGA chip layout
SmartFusion2 SoC FPGA Evaluation Board M2S090TS-EVAL-KIT
The RoHS-compliant SmartFusion®2 SoC FPGA Security Evaluation Kit (M2S090TS-EVAL-KIT) enables you to develop the following types of applications:
• Data security
• Motor control
• System management
• Industrial automation
• High-speed serial I/O applications:
• Peripheral component interconnect express (PCIe)
• Serial-gigabit media independent interface (SGMII)
• User-customizable serial interfaces
The evaluation board M2S090TS-EVAL-KIT includes: ![[Original] Microsemi Low Power SmartFusion2 SoC FPGA Development Solution](http://i.bosscdn.com/blog/14/21/33/Q04_0.png)
![[Original] Microsemi Low Power SmartFusion2 SoC FPGA Development Solution](http://i.bosscdn.com/blog/14/22/01/5031_0.png)
Figure 3. Evaluation board M2S090TS-EVAL-KIT block diagram
Main features of the evaluation board M2S090TS-EVAL-KIT:
The M2S090TS-EVAL-KIT offers a full-featured evaluation board for SmartFusion2 SoC FPGAs. Theboard integrates the following features on a single chip.
• Reliable flash-based FPGA fabric
• 166 MHz ARM Cortex-M3 processor
• Advanced security processing accelerators
• Digital signal processing (DSP) blocks
• Static random-access memory (SRAM)
• Embedded non-volatile memory (eNVM)
• High-performance communication interfaces
The SmartFusion2 Security Evaluation Board has several standard interfaces, including.
• An RJ45 connector for 10/100/1000 Mbps Ethernet
• A full-duplex serializer/deserializer (SerDes) lane connected through sub-miniature version A (SMA)connectors
• A 64-bit GPIO header
• Various connectors for serial peripheral interface (SPI) support
The SmartDesion2 memory management system supports 512 Mb on-board low-power double data rate (LPDDR) SDRAM memory and 64 Mb SPI flash memory. The SerDes block can either be accessed using the PCIe edge connector or using high-speed SMA connectors. ![[Original] Microsemi Low Power SmartFusion2 SoC FPGA Development Solution](http://i.bosscdn.com/blog/14/22/05/3911_0.png)
Figure 4. Evaluation board M2S090TS-EVAL-KIT outline drawing ![[Original] Microsemi Low Power SmartFusion2 SoC FPGA Development Solution](http://i.bosscdn.com/blog/14/22/33/2F5_0.png)
Figure 5. Evaluation board M2S090TS-EVAL-KIT circuit diagram (1) ![[Original] Microsemi Low Power SmartFusion2 SoC FPGA Development Solution](http://i.bosscdn.com/blog/14/23/01/5U6_0.png)
Figure 6. Evaluation board M2S090TS-EVAL-KIT circuit diagram (2) ![[Original] Microsemi Low Power SmartFusion2 SoC FPGA Development Solution](http://i.bosscdn.com/blog/14/23/03/4R9_0.png)
Figure 7. Evaluation board M2S090TS-EVAL-KIT circuit diagram (3) ![[Original] Microsemi Low Power SmartFusion2 SoC FPGA Development Solution](http://i.bosscdn.com/blog/14/23/41/3264_0.png)
Figure 8. Evaluation board M2S090TS-EVAL-KIT circuit diagram (4) ![[Original] Microsemi Low Power SmartFusion2 SoC FPGA Development Solution](http://i.bosscdn.com/blog/14/24/02/E58_0.png)
Figure 9. Evaluation board M2S090TS-EVAL-KIT circuit diagram (5) ![[Original] Microsemi Low Power SmartFusion2 SoC FPGA Development Solution](http://i.bosscdn.com/blog/14/24/11/5D4_0.png)
Figure 10. Evaluation board M2S090TS-EVAL-KIT circuit diagram (6) ![[Original] Microsemi Low Power SmartFusion2 SoC FPGA Development Solution](http://i.bosscdn.com/blog/14/24/43/2M9_0.png)
Figure 11. Evaluation board M2S090TS-EVAL-KIT circuit diagram (7) ![[Original] Microsemi Low Power SmartFusion2 SoC FPGA Development Solution](http://i.bosscdn.com/blog/14/25/02/a50_0.png)
Figure 12. Evaluation board M2S090TS-EVAL-KIT circuit diagram (8) ![[Original] Microsemi Low Power SmartFusion2 SoC FPGA Development Solution](http://i.bosscdn.com/blog/14/25/13/92E_0.png)
Figure 13. Evaluation board M2S090TS-EVAL-KIT circuit diagram (9) ![[Original] Microsemi Low Power SmartFusion2 SoC FPGA Development Solution](http://i.bosscdn.com/blog/14/25/44/Z51_0.png)
Figure 14. Evaluation Board M2S090TS-EVAL-KIT Circuit Diagram (10) ![[Original] Microsemi Low Power SmartFusion2 SoC FPGA Development Solution](http://i.bosscdn.com/blog/14/26/01/3649_0.png)
Figure 15. Evaluation Board M2S090TS-EVAL-KIT Circuit Diagram (11) ![[Original] Microsemi Low Power SmartFusion2 SoC FPGA Development Solution](http://i.bosscdn.com/blog/14/26/15/PZ_0.png)
Figure 16. Evaluation Board M2S090TS-EVAL-KIT Circuit Diagram (12) ![[Original] Microsemi Low Power SmartFusion2 SoC FPGA Development Solution](http://i.bosscdn.com/blog/14/26/45/10I_0.png)
Figure 17. Evaluation Board M2S090TS-EVAL-KIT Circuit Diagram (13) ![[Original] Microsemi Low Power SmartFusion2 SoC FPGA Development Solution](http://i.bosscdn.com/blog/14/2F/13/325_0.png)
Figure 18. Evaluation Board M2S090TS-EVAL-KIT Circuit Diagram (14) ![[Original] Microsemi Low Power SmartFusion2 SoC FPGA Development Solution](http://i.bosscdn.com/blog/14/2G/5R/60_0.png)
Figure 19. Evaluation Board M2S090TS-EVAL-KIT Circuit Diagram (15) ![[Original] Microsemi Low Power SmartFusion2 SoC FPGA Development Solution](http://i.bosscdn.com/blog/14/2J/C1/45_0.png)
Figure 20. Evaluation Board M2S090TS-EVAL-KIT Circuit Diagram (16) ![[Original] Microsemi Low Power SmartFusion2 SoC FPGA Development Solution](http://i.bosscdn.com/blog/14/2P/2I/14_0.png)
Figure 21. Evaluation Board M2S090TS-EVAL-KIT Circuit Diagram (17) ![[Original] Microsemi Low Power SmartFusion2 SoC FPGA Development Solution](http://i.bosscdn.com/blog/14/2S/13/4O_0.png)
Figure 22. Evaluation Board M2S090TS-EVAL-KIT Circuit Diagram (18) ![[Original] Microsemi Low Power SmartFusion2 SoC FPGA Development Solution](http://i.bosscdn.com/blog/14/2Z/19/A0_0.png)
Figure 23. Evaluation Board M2S090TS-EVAL-KIT Circuit Diagram (19) ![[Original] Microsemi Low Power SmartFusion2 SoC FPGA Development Solution](http://i.bosscdn.com/blog/14/2Z/24/100_0.png)
Figure 24. Evaluation Board M2S090TS-EVAL-KIT Circuit Diagram (20) ![[Original] Microsemi Low Power SmartFusion2 SoC FPGA Development Solution](http://i.bosscdn.com/blog/14/29/31/AB_0.png)
Figure 25. Evaluation Board M2S090TS-EVAL-KIT Circuit Diagram (21) ![[Original] Microsemi Low Power SmartFusion2 SoC FPGA Development Solution](http://i.bosscdn.com/blog/14/30/00/4607_0.png)
Figure 26. Evaluation board M2S090TS-EVAL-KIT PCB design (top screen) ![[Original] Microsemi Low Power SmartFusion2 SoC FPGA Development Solution](http://i.bosscdn.com/blog/14/30/02/WW_0.png)
Figure 27. Evaluation Board M2S090TS-EVAL-KIT PCB Design (Bottom) ![[Original] Microsemi Low Power SmartFusion2 SoC FPGA Development Solution](http://i.bosscdn.com/blog/14/30/31/3Y2_0.png)
Figure 28. Evaluation Board M2S090TS-EVAL-KIT PCB Assembly Drawing
2.0mm pin headers are board-to-board or PCB to PCB Connectors rated for 250VAC and an industry-leading current of 3.0A. Antenk offers numerous configurations for this pin header. Designed for low-profile applications, this pin header is made from high-temperature thermoplastic and is offered with several means of connections and mounting styles such as through-hole (THM) or surface mount (SMT) and can be in vertical (straight), elevated or at a right angle configuration/orientation
Automotive, Heavy Duty Military and Marine
2.0mm pitch pin headers are for not only suitable for densely packed equipment requiring weight reduction and downsizing but also for automotive connections, built to be robust in tough and harsh conditions.
Battery Connections
Rechargeable battery packs, battery balancers, battery eliminator circuits. Battery connections rely on the ability of the current to pass reliable and solid current. This prevents overheating in the circuit and voltage drop.
Medical Diagnostic and Monitoring equipment
Communications: Telecoms and Datacoms
Best used for high-reliability products that require stronger connections between layers.
Aerospace and military products are most likely to require this type of mounting as these products experience extreme accelerations, collisions, or high temperatures.
Useful in test and prototyping applications that sometimes require manual adjustments and replacements.
2.0mm vertical single row header, 2.0mm vertical dual row header, 2.0mm Elevated single row pin header, 2.0mm Elevated dual row pin Header, 2.0mm Right-angle single row header and 2.0mm Right-angle dual row header are some examples of Antenk products with through-hole mount type.
Surface-Mount
The most common electronic hardware requirements are SMT.
Essential in PCB design and manufacturing, having improved the quality and performance of PCBs overall.
Cost of processing and handling is reduced.
SMT components can be mounted on both side of the board.
Ability to fit a high number of small components on a PCB has allowed for much denser, higher performing, and smaller PCBs.
Soldering SMT pin connectors can be done at a maximum peak temperature of 260°C for maximum 60 seconds.
2.0mm pitch headers may be further classified into pin orientation as well, such as vertical or straight male header or right-angle male header.
Vertical or Straight Pin (Male) Header Orientation
One side of the series of pins is connected to PCB board in which the pins can be at a right-angle to the PCB surface (usually called "straight" or [vertical") or.
Each of these pin-types have different applications that fit with their specific configuration.
PCB Connector Stacking
Elevated Pin Header Orientation
Elevated pins aka Stacked Pins or Mezzanine are simply stacked pin headers providing an exact distance requirement between PCBs that optimizes electrical reliability and performance between PCB boards.
Profile Above PCB
This type of configuration is the most common way of connecting board-to-board by a connector. First, the stacking height is calculated from one board to another and measured from the printed circuit board face to its highest insulator point above the PCB.
Single, Dual, Triple and Four Row Number of Rows
For a 2.0mm straight or vertical male pin header, the standard number of rows that Antenk offers ranges from 1 to 4 rows. However, customization can be available if n number of rows is needed by the customer. Also, the number of contacts for the single row is about 2-40 pins. For dual row, the number contacts may vary from 2-80 pins. For triple row, it`s 2-120 pins, while for four-row, it`s 2-160 pins.
Pin Material
The pins of the connector have been designed with copper alloy. With customer`s demand the pins can be made gold plated.
Breakaway design
The pin headers are also equipped with a breakaway design making them fully compatible with their female receptacles.
Custom 2.0mm Pitch Pin Headers
Customizable 2.0 mm pitch pin headers are also available, making your manufacturing process way faster as the pins are already inserted in the headers, insulator height is made at the right size and the accurate pin length you require is followed.
Parts are made using semi-automated manufacturing processes that ensure both precision and delicacy in handling the headers before packaging on tape and reel.
Tape and Reel Packaging for SMT Components
Antenk's SMT headers are offered with customizable mating pin lengths, in which each series has multiple number of of circuits, summing up to a thousand individual part number combinations per connector series.
The tape and reel carrier strip ensures that the headers are packaged within accurately sized cavities for its height, width and depth, securing the headers from the environment and maintaining consistent position during transportation.
Antenk also offer a range of custom Tape and reel carrier strip packaging cavities.