The embedded Nios II soft-core multi-processor system based on SoPC technology has independent design, good reconfiguration, easy software and hardware cutting, convenient system expansion and upgrade, and can balance performance, volume, power consumption, cost and reliability. Requirements. The development of embedded Nios II soft multiprocessor system is an effective way to improve the cost performance and practicality of embedded systems. The core of the embedded system is the RISC processor, and the representative RISC soft core processor is the Nios II processor. A soft core processor is a processor that is generated programmatically. It is a new technology that combines hardware logic, intelligent algorithms, hardware description language and programming to design processor hardware circuits. The advantage of the on-chip Nios II embedded multiprocessor system is that the designer can choose the type and number of Nios II processors and set them according to the actual needs, optimize the memory and peripheral devices, and maximize the on-chip resources and Utilization of system resources. 1.1 Nios II processor The system built by the Nios II soft core processor can easily cut the system hardware and software, and can be integrated on an FPGA chip. The system and real-time evaluation are very fast and convenient, which can greatly shorten the design cycle and reduce the design risk. 1.2 Multiprocessor System Type According to shared resources, there are two types of non-shared resource multiprocessor systems and shared resource multiprocessor systems. Non-shared resources Multiple Nios II processors in multiple processor systems are completely independent, do not share system resources, and the processors do not interfere with each other, and the system structure is not too complicated. Shared Resource Multiprocessor Systems In order to ensure the safe and reliable operation of multiple Nios II processors in the case of shared resources, it is beneficial to improve the performance, volume, cost and power consumption of each processor, but the system The design of the software is more complicated. According to the processor topology, there are two types, one is non-hierarchical structure, the connection between the processor and the system components is easy; the other is the hierarchical structure, which can determine the number of Nios II processors according to actual needs, and optimize the internal of the system. Structure to effectively utilize the resources of the FPGA chip. But there are problems with balancing the load and task coordination of multiple processors. A plurality of Nios II soft core processors, a set of on-chip peripheral interfaces, on-chip memories, off-chip memory interfaces, etc. are integrated on an FPGA chip to form the basic architecture of the on-chip embedded Nios II soft multiprocessor system. 2.1 Sharing System Resources The Nios II multiprocessor system shares memory and peripheral system resources. In order to ensure that each processor shares resources, preventing program or data errors due to interference between processors, the entire system crashes. The Nios II multiprocessor system uses hardware mutual exclusion core components to protect shared resources to coordinate the normal operation of each processor and ensure uninterrupted interference between processors, thereby improving the performance of multiprocessor systems. 2.2 Hardware Mutual Nucleus The hardware mutual exclusion core is used to coordinate the access of each processor to shared resources. The hardware mutual exclusion core has no internal functions and is a simple QSYS component. It provides a protocol to guarantee mutual exclusion of ownership of shared resources. Only one processor allows access to shared hardware resources at any time, so as to effectively protect multiple processors from accessing hardware resources and preventing data corruption. Or the system crashes. The mutex kernel mutex provides an atomic test and set operation that allows the processor to test, and if the mutex is available, obtain a mutex processor for a single operation. When the processor finishes using shared peripherals and mutex locks, the mutex is released. Thereafter, another processor can acquire the right to use the mutex and the shared peripheral. Pc Material,Pc Plastic Material,Pc Clear Material,Pc Material Properties WENZHOU TENGCAI ELECTRIC CO.,LTD , https://www.tengcaielectric.com
It should be noted that the mutual exclusion core does not have the physical protection that the peripheral system is accessed by multiple processors at the same time. The software running on the processor is responsible for complying with the mutual exclusion protocol. After the software acquires the mutex by writing, the processor accesses it. Shared peripherals. Multiple processors access a mutex core, and each processor has a unique identifier ID (cpuid). Altera provides subroutines for the Nios II processor access hardware. These functions are for the mutex core and operate directly on the underlying hardware. Each processor writes the value of its cpuid control register to the owner field of the mutex register. Locks, while mutex cannot access the HAL API or the ANSI C standard library.