Summary of high-speed PCB design rules and analysis of causes (graphics)

**Foreword** Designing high-speed systems goes beyond just using fast components; it requires a deep understanding of the design process and meticulous attention to detail. Device simulation plays a crucial role in ensuring the reliability and performance of such systems, much like the digital aspects of the design. In high-speed environments, noise becomes a critical factor that must be addressed. High frequencies can lead to electromagnetic interference (EMI), while fast signal edges may cause ringing, reflections, and crosstalk. If not properly managed, these issues can severely impact system performance. **First, achieving efficient PCB design and automatic routing** Although modern EDA tools are powerful, as PCBs become smaller and more densely packed, the challenges of design have increased. The goal is to achieve higher throughput and reduce design time. This article outlines key strategies for planning, layout, and routing in PCB design. With shrinking board sizes, tighter rules, and larger components, the designer's workload has grown significantly. Many manufacturers now rely on specialized EDA tools, but these often fall short of expectations, leading to messy results and lengthy manual adjustments. There are numerous EDA tools available, but they share similar functionalities. The real challenge lies in how effectively these tools can be utilized. A careful analysis of the design and proper configuration of the software before starting the routing process can greatly improve the quality and compliance of the final product. Below are some general guidelines for PCB design: 1. **Determine the number of PCB layers** The number of layers and board size should be decided early in the design phase. For high-density BGA components, the minimum number of routing layers must be considered. The layer count and stack-up directly affect trace impedance and routing feasibility. Proper planning at this stage can prevent last-minute changes and unnecessary complexity. 2. **Set up design rules and constraints** Autorouting tools require clear instructions. Different signal types have different requirements, and each class of signals should be prioritized accordingly. Rules regarding trace width, via count, parallelism, and layer restrictions significantly influence routing success. Careful setup ensures smoother automation and better results. 3. **Component placement** DFM (Design for Manufacturability) rules dictate component placement. If allowed, moving components can optimize the layout for easier routing. Constraints from design rules also play a role in determining where and how components are placed. 4. **Fanout design** During fanout, each pin of a surface-mount device must have at least one via to enable inner-layer connections, testing, and rework. Using large vias and spacing them appropriately helps maximize routing efficiency. Consideration of online testability is essential, as adding test points later can be costly and time-consuming. 5. **Manual wiring and critical signal handling** While automated routing is valuable, manual intervention is still necessary for critical signals. By manually routing key nets first, designers can create reliable paths that help the automated tool complete the rest of the work. After verification, these signals are fixed, and the remaining ones are routed automatically. 6. **Automatic routing** Routing critical signals involves managing electrical parameters like inductance and EMC. EDA vendors provide various ways to control these factors. Understanding input parameters and their impact on routing ensures better outcomes. General rules should guide the routing process, with constraints set to align with the engineer’s design philosophy. 7. **Wiring optimization tips** - Slightly adjust settings and try multiple routing paths. - Keep basic rules consistent, but experiment with different layers, trace widths, and via types. - Let the tool handle default networks. - Less important signals can be routed with more flexibility. 8. **Finalizing the wiring** Review the routing length and make manual adjustments if needed. Ensure that all traces are reasonable and meet design criteria. This step helps refine the design and improve overall performance. 9. **Board aesthetics** While visual appeal is less important today, the design must meet electronic specifications. Automated boards may not look as clean as manually designed ones, but they perform reliably. **Second: High-Speed PCB Design – Solving 9 Rules of EMI Problems** As signal rise times decrease and frequencies increase, EMI becomes a growing concern for engineers. High-speed PCB design plays a major role in controlling EMI, with about 60% of EMI issues being addressable through proper PCB layout. Here are nine key rules to follow: 1. **Shield high-speed signal traces** Critical signals like clocks should be shielded. Shielding every 1000 mils helps prevent EMI leakage. 2. **Avoid closed-loop routing** Closed loops can act as loop antennas, increasing EMI radiation. Avoid creating such structures during multi-layer routing. 3. **Avoid open-loop routing** Open loops can also radiate, acting as linear antennas. Ensure that high-speed signals do not form open-ended traces. 4. **Maintain continuous characteristic impedance** Impedance discontinuities between layers increase EMI. Ensure consistent trace widths and impedances across layers. 5. **Use vertical routing between adjacent layers** Horizontal and vertical routing reduces crosstalk and EMI. Vertical routing between layers suppresses interference. 6. **Use proper topology for high-speed signals** Star-shaped topologies are preferred over daisy chains for high-speed designs to minimize signal distortion. 7. **Avoid resonant trace lengths** Trace lengths that are multiples of 1/4 wavelength can resonate, causing EMI. Check signal lengths against frequency to avoid resonance. 8. **Ensure a good return path** All high-speed signals must have a low-impedance return path. Minimize the area between the signal and return path to reduce radiation. 9. **Place decoupling capacitors close to power pins** Capacitors should be placed near the power supply pins, with minimal area enclosed by the power and ground traces for optimal filtering. **Third: Summary of High-Speed PCB Design Rules and Their Causes** 1. **Multi-layer boards are required when clock frequency exceeds 5MHz or rise time is less than 5ns** Multi-layer boards allow better control of signal loop areas, reducing EMI. 2. **Key signal lines should be adjacent to ground planes** Placing critical signals near ground planes minimizes radiation and improves immunity. 3. **Single-layer boards should have grounded shields around key signals** Grounding both sides of the signal line reduces loop area and prevents crosstalk. 4. **Double-layer boards should have large ground planes under key signals** Large ground planes help suppress edge radiation and maintain signal integrity. 5. **Power planes should be recessed relative to ground planes** Recessing power planes reduces edge radiation and improves signal performance. 6. **Wiring layers should be within the projected area of the reference plane** Avoiding off-center routing reduces loop area and differential mode radiation. 7. **High-frequency signals should not be on outer layers** Moving high-frequency signals between internal planar layers reduces external radiation. 8. **Top and bottom layers should be grounded if operating frequency exceeds 50MHz** Grounding outer layers suppresses high-frequency radiation. 9. **Power and ground planes should be adjacent** Proximity reduces power loop area and improves stability. 10. **Ground lines should be placed near power lines on single-layer boards** Reducing power loop area minimizes EMI. 11. **Double-layer boards should also have ground lines near power lines** Same reasoning applies—minimizing loop area is essential. 12. **Avoid adjacent wiring layers if possible** Parallel traces can cause crosstalk, so widening the spacing between layers is recommended. 13. **Avoid overlapping projection planes between adjacent layers** Overlapping can cause coupling capacitance and noise between layers. 14. **Follow signal flow direction during layout** Avoid back-and-forth routing to prevent signal coupling and degradation. 15. **Separate analog, digital, high-speed, and low-speed circuits** Preventing interference between different circuit types improves overall performance. 16. **Keep high-speed circuits away from interfaces** Reduces the risk of noise escaping through cables or connectors. 17. **Place energy storage and high-frequency filter capacitors near high-current areas** Minimizes loop area and reduces EMI. 18. **Filter circuits should be placed near the power input** Prevents recoupling of already filtered signals. 19. **Interface circuits should be close to the actual interface** Ensures effective filtering, protection, and isolation. 20. **Protective circuits should come before filters** Protects filters from damage due to overvoltage or overcurrent. 21. **Input and output lines of filters should not couple** Coupling weakens the effectiveness of filtering, protection, and isolation. 22. **Place filtering and isolation devices on the "clean" side of the interface** Prevents coupling through plane layers and maintains signal integrity. 23. **No other components should be placed on the "clean" side** Ensures minimal interference and clean signal paths. 24. **Strong radiation sources should be kept away from interface connectors** Reduces direct radiation and cable-coupled EMI. 25. **Sensitive circuits should be placed away from board edges** Boards are prone to static and external interference, especially at edges. 26. **Decoupling capacitors should be close to IC power pins** Smaller loop area means less radiation and better filtering. 27. **Series matching resistors should be placed near the signal source** Ensures proper impedance matching at the source end. 28. **Avoid right-angle or sharp corners on traces** Sharp corners cause impedance discontinuities, leading to EMI and signal distortion. 29. **Avoid parallel traces on adjacent layers if possible** Reduce crosstalk by keeping traces perpendicular or limiting their length. 30. **Place key signals on internal layers** Internal layers offer better shielding and reduced EMI. 31. **Ground lines should be placed on both sides of clock lines** Grounding every 3000 mils ensures equal potential and reduces noise. 32. **Parallel lines on the same layer should follow the 3W rule** Avoids crosstalk between signals. 33. **High-current components should have at least two vias connected to the plane** Reduces via impedance and improves current flow. 34. **Differential pairs should be on the same layer, equal length, and without other traces in between** Maintains balanced impedance and improves noise immunity. 35. **Critical signals should not cross plane partitions** Crossing partitions increases loop area and EMI. 36. **Use bridge capacitors when unavoidable** Helps maintain a stable return path across partitioned areas. 37. **Avoid unrelated traces under filter circuits** Distributed capacitance can weaken the filter’s effectiveness. 38. **Filter input and output lines should not be parallel or cross-routed** Prevents direct noise coupling after filtering. 39. **Critical signals should be at least 3H away from the reference plane edge** Suppresses edge radiation and improves signal integrity. 40. **Metal case grounding should be placed on the top layer under the projection area** Improves immunity and reduces external noise coupling. 41. **Single or double-layer boards should use minimal loop area design** Smaller loops mean less radiation and better immunity. 42. **Vias should be placed near layer transitions** Reduces signal loop area and improves routing efficiency. 43. **Strong radiation signals should be kept away from outgoing interface signals** Prevents interference and unwanted radiation. 44. **Sensitive signals should be isolated from outgoing interface signals** Avoids system malfunctions caused by external interference. 45. **Filter capacitors should be placed before the device pin** Ensures clean power delivery and noise filtering. 46. **Long power lines should include coupling capacitors every 3000 mils** Filters out high-frequency noise and stabilizes the power supply. 47. **Filter capacitor grounding and power lines should be thick and short** Reduces inductance and improves high-frequency performance.

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