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In recent years, the exploration of using CMOS processes in radio frequency (RF) applications has seen a significant rise. With the advancement of deep submicron technology, CMOS circuits are now capable of operating at frequencies exceeding 1 GHz, which has greatly accelerated the development of integrated RF circuits based on CMOS. Various research groups have successfully developed high-performance downconverters, low-phase-noise voltage-controlled oscillators (VCOs), and dual-modulus prescalers using standard CMOS fabrication. These achievements demonstrate that fully integrated receiver and VCO circuits can be designed without the need for external components or adjustments. Further research into low-noise amplifiers, upconverters, synthesizers, and power amplifiers is expected to lead to the creation of fully integrated transceiver CMOS RF circuits suitable for telecommunications.
The rapid growth of wireless communication and its associated technologies has been largely driven by the integration of digital coding and signal processing techniques. The evolution of digital technology has been made possible by the development of high-performance, low-cost CMOS technology, which enables the integration of numerous digital functions onto a single chip. This advancement allows for the implementation of advanced modulation schemes, complex demodulation algorithms, and high-quality error detection and correction systems, resulting in a highly efficient and lossless digital communication channel.
Currently, the progress in digital technology and the expansion of the wireless market have significantly transformed analog transceiver front-end equipment. The front-end serves as the interface between the antenna and the digital modem in a wireless transceiver. It must detect weak signals in the range of microvolts at frequencies from 1 GHz to 2 GHz while simultaneously transmitting signals with about 2 W of power at the same high frequency. This requires high-performance analog components such as filters, amplifiers, and mixers that can efficiently convert between the antenna's frequency band and the A/D conversion and digital signal processing stages. Due to the demand for low cost and low power consumption, the analog front-end has become a critical bottleneck in future RF designs. Further improvements in integration will help reduce die size, cost, and power consumption. Over the past few years, various techniques have been proposed to enhance the integration of receivers, transmitters, and synthesizers.
As the level of integration continues to increase, researchers are also exploring the possibility of integrating RF circuits within a CMOS process. While CMOS is primarily used for digital circuit integration, applying it to high-performance analog circuits could offer substantial benefits. A complete transceiver can be integrated on a single chip, combining both the analog front-end and digital demodulator on the same die. This can only be achieved using CMOS or BiCMOS processes. Although BiCMOS offers better analog performance, it comes at a higher cost due to increased per-unit-area costs and the need for more chip space for digital components. As investment in CMOS processes far exceeds that in bipolar devices, common CMOS processes are gradually replacing BiCMOS in NMOS-based designs using deep submicron CMOS. Even in the same BiCMOS process, performance differences between NMOS and BJT devices are diminishing, with the ft parameter of NMOS devices approaching that of NPN transistors.
Although early studies on RF design using CMOS technology date back many years, it is only in recent times that the potential of this approach has gained real attention. Several industry research groups are actively working on this topic. Some researchers believe that RF CMOS is suitable only for low-performance systems, such as ISM bands, or can be improved through techniques like under-etched inductors. However, RF CMOS technology is expected to enable the full integration of high-performance applications like GSM, DECT, and DCS1800 in a common deep submicron process.
**CMOS Technology**
Submicron technology is now considered standard CMOS due to the increasing demands for higher integration and advanced digital signal processing (DSP) circuits. This trend has evolved into deep submicron technology, with transistors featuring specifications below 0.1 microns. Recently, transistors with ft values close to 100 GHz have emerged in 0.1-micron deep submicron processes.
However, parasitic capacitance in transistors—such as gate-drain overlap capacitance and drain-bulk junction capacitance—has posed challenges to further development in deep submicron technology. Figure 1 compares the ft and fmax values across different technologies, clearly illustrating the impact of these parasitics. While ft increases rapidly, the actual circuit performance (fmax) does not improve as significantly. This highlights the importance of fmax in real-world applications.
Finally, it has become evident that in recent integrated CMOS RF circuits, both the CMOS technology itself and the packaging play a limiting role. Since RF signals originate from the chip, and the RF antenna signal must enter the chip, any parasitic capacitance from PCB or package pins connected to the ESD protection network can severely degrade the RF signal quality.
**Receiver Topology**
The most commonly used receiver architecture is the heterodyne or intermediate frequency (IF) receiver. In an IF receiver, the desired signal is downconverted to a relatively high intermediate frequency. A high-quality passive bandpass filter is used to prevent the image signal from overlapping with the desired signal at the IF frequency. By employing multiple IF stages, extremely high receiver performance can be achieved.