STM32 Watchdog Time Calculation (TWDG): 1.STM32 watchdog example The time of the IWDG is limited to 280 microseconds. This time limit may occur with the frequency drift of the LSI (internal low-speed clock). Small changes. /* IWDG TImeout equal to 280 ms (the TImeout may vary due to LSI frequency Dispersion) ------------------------------------------------ ------------- */ /* Enable write access to IWDG_PR and IWDG_RLR registers */ IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable); /* IWDG counter clock: 40KHz (LSI) / 32 = 1.25 KHz */ IWDG_SetPrescaler(IWDG_Prescaler_32); /* Set counter reload value to 349 */ IWDG_SetReload(349); /* This parameter allows the value range to be 0 – 0x0FFF * /* Reload IWDG counter */ IWDG_ReloadCounter(); /* Enable IWDG (the LSI oscillator will be enabled by hardware) */ IWDG_Enable(); 2. The Independent Watchdog (IWDG) is driven by a dedicated 40kHz low-speed clock; therefore, it remains active even if the primary clock fails. The window watchdog is driven by a clock derived from the APB1 clock divider and uses a configurable time window to detect unusual or premature behavior of the application. accessible IWDG_SetPrescaler(IWDG_Prescaler_32); divides its clock, 4-256, Feed the dog by: /* Reload IWDG counter */ IWDG_ReloadCounter(); 3. 1.25KHz is 0.8ms per cycle A total of 350 cycles, ie 350*0.8ms=280ms In summary, the STM32 watchdog time (time limit) and frequency calculation formula is: Watchdog timing limit = value of IWDG_SetReload() / watchdog clock frequency Watchdog clock frequency = LSI (internal low-speed clock) frequency (40KHz) / frequency division Stm32 independent watchdog and window watchdog features, differences: To sum up, the two have the following characteristics and differences: 1) The independent watchdog is not interrupted, and the window watchdog is interrupted. 2) Independent watchdog has hardware and software, window watchdog can only be controlled by software 3) Independent watchdog has only lower limit, window watchdog has lower limit and upper limit 4) The independent watchdog is 12-bit descending. The window watchdog is 7-digit decreasing 5) The independent watchdog is used internally for approximately 40KHZ RC oscillator, the window watchdog is used for the system clock APB1ENR I will give you a detailed introduction below: The independent watchdog has no interrupt function. As long as the value of the counter is reloaded before the counter is reduced to 0 (lower limit), no reset will be generated. The independent gate can be divided into hardware and software. The hardware is passed through the programmer. Set options, etc. "Configuration, once the hardware watchdog is turned on, then it can't stop, only reconfigure "set options, etc." to turn off the hardware watchdog, software watchdog only Need to set IWDG->KR=0XCCCC; you can start the watchdog, the dongle can be turned off during system reset, if you open the software watchdog in the initialization, then open the software watchdog, independent gatekeeper The dog is a 12-bit decrementing register that uses the RC oscillator inside the chip. This oscillator cannot be turned off. The window watchdog has an interrupt. The function of this interrupt is to generate an interrupt when the counter reaches the lower limit of 0x40. Let you feed the dog. If you don't feed the dog, the counter value will become 0x3f, and a system reset will occur, even if Is to feed the dog, should also quickly feed the dog in the interrupt, or not long time the counter minus one will become 0x3f to generate a reset, this time can be calculated according to the formula of the chip manual, the window watchdog only software open mode There is also an upper limit value. If the value is greater than the initial value of the counter, then there is no effect. When the value is less than the initial value of the counter, when the value of the counter is greater than the upper limit, you will load the counter. A reset is generated, and you can reload the counter only when the counter is reduced to less than the upper limit, meaning that only the counter value can be loaded between the upper and lower limits, otherwise a system reset will occur. It does not make sense that the upper limit is less than the lower limit. Independent Watchdog Iwdg - My understanding is that it is independent of the system, because there is an independent clock, so the system is not affected by the system fault detector. Mainly used to monitor hardware errors. Window watchdog wwdg - my understanding is the fault detector inside the system, the clock is the same as the system. If the system clock does not go away, the dog will lose its effect. Mainly used to monitor software errors. The following are discovered after testing: / / Found 1: When the window value is greater than or equal to the value of the counter, no matter how to change the order of configuration, are the correct running results //Discover 2: When the window value is less than the value of the counter, the operation will be wrong once the order is changed. After testing, it was found that when the order of initialization is not in the normal order, WWDG->SR will be set to one. Why don't I know who knows what to do in the film. When you open the interrupt, you enter the interrupt. At this time, if you feed the dog again, it will be reset. Because the value of the counter is the value of the upper limit window, it will be reset, so it will continue to go wrong. The solution is that the last two sentences of the initial words are to clear the interrupt flag and then enable the interrupt. If you don't do this, then it is possible to set WWDG->SR during initialization, then you will open the interrupt. Without hesitation, you enter the interrupt, and when you interrupt the reload counter, it will generate a reset. Din Connector,Waterproof Cable Connector,Ip66 Wire Waterproof Connector,Waterproof Power Connector Shenzhen Hongyian Electronics Co., Ltd. , https://www.hongyiancon.com