The basic principle of phase-locked loop, phase model and transfer function of phase-locked loop
Phase locking refers to the automatic control of phase synchronization between two signals. A closed-loop system designed to achieve this synchronization is known as a Phase-Locked Loop (PLL). PLLs are widely used in various technical fields, including broadcast communication, frequency synthesis, automatic control, and clock synchronization. A typical PLL system consists of three main components: a phase detector (PD), a voltage-controlled oscillator (VCO), and a low-pass filter (LPF), as illustrated in Figure 1.
The phase detector compares the phase of two input signals and generates an output that reflects their phase difference. One common type of phase detector used in experiments is the XOR gate-based detector. Its truth table is shown in Table 1, and its logic symbol is presented in Figure 2. As demonstrated, when both input signals have a 50% duty cycle, the output waveform’s duty ratio depends on the phase difference Δθ. By passing this signal through an integrator, we can extract the average DC value, which is proportional to Δθ. This allows the XOR gate to function as a phase-to-voltage converter, forming a basic phase detection circuit.
The relationship between the DC output voltage and the phase difference is linear, expressed as:
U = Vdd × Δθ / π
This equation shows that the DC component varies with the phase difference. The proportionality constant, Kd, represents the phase sensitivity of the detector. The relationship between Δθ and the output voltage Ud is shown in Figure 3, confirming the linear behavior.
Another type of phase detector is the edge-triggered one, which compares the rising or falling edges of the input signals rather than their full waveforms. This design eliminates the need for a 50% duty cycle, making it more versatile in practical applications.
Next, the voltage-controlled oscillator (VCO) adjusts its oscillation frequency based on an input control voltage. The instantaneous frequency ω₀(t) is given by:
ω₀(t) = ωₘ + K₀ × UF(t)
Here, ωₘ is the free-running frequency, and K₀ is the VCO's control sensitivity. This makes the VCO act as a voltage-to-frequency converter, essential for maintaining phase alignment within the loop.
The loop filter smooths the error signal from the phase detector and ensures stability. A passive proportional-integral filter, as shown in Figure 5, has a transfer function that determines how the loop responds to changes in phase and frequency. This component plays a crucial role in shaping the dynamic behavior of the PLL.
To understand the operation of a PLL, we analyze its phase model and transfer function. These models help predict the system’s response under different conditions. The block diagram in Figure 6 illustrates the feedback mechanism, while Figures 7–11 provide additional details on the mathematical representation of the loop.
Finally, the concepts of synchronization and capture are important in understanding how a PLL maintains lock. In the synchronized state, the VCO frequency ω₀ matches the input frequency ωᵢ. The range over which this synchronization can be maintained is called the synchronization bandwidth (Δω_H). If the input frequency deviates beyond this range, the loop loses lock. However, if the frequency is gradually adjusted back toward the VCO frequency, the loop may re-lock, entering the capture band (Δω_p). The relationship between these frequencies and the VCO center frequency is shown in Figure 12.
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