The basic principle of phase-locked loop, phase model and transfer function of phase-locked loop
Phase locking refers to the automatic control of phase synchronization between two signals. A system that can achieve and maintain this synchronization is known as a Phase-Locked Loop (PLL). PLLs are widely used in various technical fields such as communication systems, frequency synthesis, automatic control, and clock synchronization. A basic PLL typically consists of three main components: a phase detector (PD), a voltage-controlled oscillator (VCO), and a low-pass filter (LPF), as illustrated in Figure 1.
The phase detector compares the phases of two input signals and generates an output proportional to their phase difference. One common type is the XOR gate-based phase detector, which works effectively when both input signals have a 50% duty cycle. The truth table for the XOR gate is shown in Table 1, along with its logical symbol in Figure 2. When there's a phase difference Δθ between the two input signals, the output waveform’s duty cycle depends on this difference. By integrating the output signal using an integrator, we obtain a DC component that is proportional to Δθ, allowing the XOR gate to function as a phase-to-voltage converter. The average value after integration can be expressed as:
$$ U = V_{dd} \cdot \frac{\Delta\theta}{\pi} $$
This relationship shows a linear dependence between the phase difference and the DC output voltage, given by:
$$ U_d = K_d \cdot \Delta\theta $$
where $ K_d $ is the phase sensitivity. This linear behavior is illustrated in Figure 3.
Another type of phase detector is the edge-triggered one, which compares only the rising or falling edges of the input signals, eliminating the need for a 50% duty cycle. This makes it more versatile in practical applications.
The voltage-controlled oscillator (VCO) adjusts its output frequency based on an input control voltage. Its operation can be described by the equation:
$$ \omega_o(t) = \omega_{om} + K_0 \cdot U_F(t) $$
where $ \omega_{om} $ is the free-running frequency, and $ K_0 $ represents the VCO’s control sensitivity. This allows the VCO to act as a voltage-to-frequency converter.
The loop filter, often a passive proportional-integral filter, smooths the output of the phase detector and helps stabilize the system. Its transfer function is given by:
$$ H(s) = \frac{R_2}{R_1 + R_2} \cdot \frac{1}{1 + sC(R_1 + R_2)} $$
This filter plays a crucial role in shaping the dynamic response of the PLL.
In terms of the phase model and transfer function, the overall system can be represented in the frequency domain. The closed-loop transfer function of the PLL is derived from the combination of the PD, VCO, and loop filter. These models help analyze the stability and performance of the system under different conditions.
When a PLL is in a locked state, the output frequency of the VCO matches the input frequency. The range within which the input frequency can vary while maintaining lock is called the **locking bandwidth** $ \Delta\omega_H $. If the input frequency deviates beyond this range, the loop loses lock. However, if the frequency is slowly adjusted back into the range, the loop can reacquire lock. The frequency range over which the loop can capture and lock onto the input signal is known as the **capture bandwidth** $ \Delta\omega_p $.
The relationship between these parameters and the VCO center frequency $ \omega_o $ is illustrated in Figure 7, showing how the system behaves under different frequency conditions. Understanding these concepts is essential for designing and analyzing PLL systems in modern communication and control applications.
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