Data storage The data memory consists of a Special Function Register (SFR) and a General Purpose Register (GPR). The SFR controls the operation of the device, while the GPR is a common area for data storage and rewriting. The SFR and GPR data stores are divided into different storage areas. GPR is divided into different memory areas to achieve addressing of more than 96 bytes of general purpose RAM. SFRs are registers used to control peripheral and core functions. The bank select control bits (STATUS<7:5>) of the STATUS register are used to select the bank. Figure 6-5 shows the composition map of the data memory, which is related to the part number. When transferring data from one register to another, it must pass through the W register. This means that two data cycles are required for data transfer between all registers. The entire data memory can be accessed using direct or indirect addressing. Direct addressing may require the use of RP1, RP0 bits, and indirect addressing requires the use of a pointer register (FSR). The Indirect Register Pointer (IRP) bit of the Status Register is used when indirectly addressing Memory Area 0/Memory Area 1 or Memory Area 2/Memory Area 3 of the Data Memory. General purpose register (GPR) The GPR of some mid-range microcontrollers is divided into different memory areas. The power-on reset does not initialize the GPR. Other resets cannot change the value of GPR. The registers can be addressed either directly or indirectly using the pointer register FSR. Some devices have a common data storage area shared by each data storage area. The reading and writing of the common data storage area does not need to consider the current storage area. The same address unit (value) can be used. We call this area public RAM. Special Function Register (SFR) Special function registers are used by the CPU and peripherals to control the operation of the device. These registers are implemented as static RAM. Special function registers can be divided into two categories, one related to kernel functions and the other related to peripheral functions. This chapter describes the special function registers associated with the core functions. Another type of special function registers related to the operation of peripheral functions is described in the corresponding peripheral function module chapter. The SFR register area of ​​all mid-range microcontrollers is also divided into different memory areas. When switching between these memory intervals, you need to set the RP0 and RP1 bits of the status (STATUS) register to select the desired memory area. Some SFR registers are initialized by a power-on reset and other resets, and some SFR registers are not initialized on reset. *Note: There may be general purpose registers mapped to the Special Function Register area. Registers can be addressed either directly or indirectly via a pointer register. Storage division The data memory is divided into four memory areas, each of which includes special function registers and general purpose registers. To use direct addressing, to switch between these banks, you need to set the RP0, RP1 bits of the status register to select the desired bank. The IRP bit of the Status Register is used for indirect addressing. Each bank can have up to 128 bytes (7FH). The special function registers are arranged in the lower address unit of the memory area; the general purpose registers are arranged in the high address unit. All data memory uses static RAM. All memory areas include special function registers. In order to reduce the program code and increase the access speed, some special function registers in the memory area 0 are mapped in other memory areas. As the product evolves, there are some changes in the design layout of its data memory. For all new devices, the standard data memory is shown in Figure 6-5. In this memory map, the last 16 bytes of all banks are mapped into bank 0, which can reduce the software overhead for field switching. The registers in bold are present in each microcontroller, and the presence or absence of other registers is related to the peripheral modules. Not all of the peripheral registers are shown in the figure because the register definitions at certain file addresses are different for the different devices. In addition to using all the diagrams, tables and instructions provided in this manual, you should also refer to the specific device data sheet to verify the details. MARSHINE Hydraulic Compressor Feature:
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